The present invention is directed to a digital to analog converter (xe2x80x9cDACxe2x80x9d) that includes a main section of the DAC to convert a most significant bit portion of the digital input and a sub-DAC to convert a least significant bit portion of the digital input. More particularly, the present invention is directed to a digital to analog converter (xe2x80x9cDACxe2x80x9d) that includes a main section of the DAC to convert a most significant bit portion of the digital input and a sub-DAC to convert a least significant bit portion of the digital input wherein a gain of the sub-DAC matches and tracks the gain of the main section of the DAC.
Multicarrier radio architectures have conventionally used a single lower resolution digital to analog converter (xe2x80x9cDACxe2x80x9d) per carrier at a low baseband frequency followed by an analog channel combine and mix to an intermediate frequency (xe2x80x9cIFxe2x80x9d) and then to a radio frequency (xe2x80x9cRFxe2x80x9d). FIG. 1 illustrates a simple block diagram showing a conventional transmit architecture.
As illustrated in FIG. 1, a plurality of DACs 1, each corresponding to a separate carrier, receives digital data and converts the received signal into analog signals. The analog signals are combined in combiner 2 prior to being mixed with an intermediate frequency by intermediate frequency mixer 3. Thereafter, the mixed signal is further mixed with a radio frequency by a radio frequency mixer 4. It would be desirable to use a single higher resolution digital to analog converter in this application. However, there have been limits to achieving the necessary resolution. It is the aim of the present invention to address one such limit.
FIG. 2 illustrates an example of a conventional digital to analog converter 10 (xe2x80x9cDAC 10xe2x80x9d) used in the low resolution DACs of FIG. 1. The DAC 10 includes a plurality of unit cells 12, 12l . . . 12n. Each cell, illustrated with respect to cell 12, includes a current source 14, a trim circuit 16, a calibration switch 18, and a current output switch 20. All of the output switches provide their analog outputs on the analog output network 22 where the analog outputs are summed.
Each calibration switch 18 connects a current source 14 either over line 24 to the associated output switch 20 or over line 26 to a calibration reference circuit 28. Calibration reference circuit 28 communicates over line 30 with each of the trim circuits 16 communicating to each of them the amount of current that must be added or subtracted to the output current on line 32 from current source 14 to ensure that the output current from each of the current sources 14 in each of the cells 12, 12l, . . . 12n, are equal.
A control signal on line 34 sets calibration switch 18 either to the load mode where it connects current source 14 over line 24 to output switch 20 or over line 26 to calibration reference circuit 28 in the calibration mode. Each output switch 20 in addition to providing its output current on line 38 to analog output network 22 receives at its input data on lines 40 and 42.
FIG. 3 provides a more detail schematic of the digital to analog converter of FIG. 2. As illustrated in FIG. 3, an analog reference signal is fed to a plurality of current source transistors (M1, M2, . . . , M3, M4). Each current source transistor (M1, M2, . . . , M3, M4) is connected to current source bias circuit 15. As illustrated in FIG. 3, the digital signal is segmented between a most significant bit (xe2x80x9cMSBxe2x80x9d) section and a least significant bit (xe2x80x9cLSBxe2x80x9d) section, wherein the LSB section is a sub-DAC.
To implement this segmentation, the output of each current source transistor associated with the MSB section (in FIG. 3, these current source transistors are M1, M2, . . . , M3) is connected to a digital to analog converter output switch (20a, 20b, . . . , 20c). More specifically, the output of each current source transistor associated with the MSB section is connected to an isolation cascode transistor (M5, M6, . . . , M7) within the respective digital to analog converter output switches (20a, 20b, . . . , 20c).
Moreover, the output of the current source transistor associated with the LSB section (in FIG. 3, this current source transistor is M4) is connected to a plurality of digital to analog converter output switches (20d, 20e, . . . , 20f). More specifically, the output of the current source transistor associated with the LSB section is connected to a plurality of isolation cascode transistors (M8, M9, . . . , M10) within the respective digital to analog converter output switches (20d, 20e, . . . , 20f).
Each isolation cascode transistor (MS, M6, . . . , M7, M8, M9, . . . , M10) is connected to cascode bias circuit 104. Moreover, each output switch (20a, 20b, . . . , 20c, 20d, 20e, . . . , 20f) in addition to providing output current on lines 38 to analog output network 22 receives at its input data on lines (40a, 42a, 40b, 42b, 40c, 42c, 40d, 42d, 40e, 42e, 40f, and 42f).
The approach illustrated in FIG. 1 has been conventionally utilized in view of the DAC""s intermodulation distortion (xe2x80x9cIMDxe2x80x9d) limiting the dynamic range of the DAC. However, as carriers are added, the peak power remains the same, but the average power reduces by 10-log (# of carriers). Moreover, as carriers are added, spectral emissions of the composite-multicarrier output must still be maintained on a per carrier basis, requiring a larger dynamic range from the DAC and thus the need for higher resolution. Furthermore, where large peak to average ratios are used it is possible, in some modulation schemes, for the absolute noise power spectral density (xe2x80x9cNSDxe2x80x9d) of the DAC to limit the dynamic range of the DAC.
Therefore, it is desirable to provide a digital to analog converter that does not experience limitations to its dynamic range as carriers are added. In other words, it is desirable to provide a DAC wherein the DAC has IMD and NSD sufficient to meet multicarrier demands.
A first aspect of the present invention is a digital to analog converter circuit. The digital to analog converter circuit includes a main digital to analog converting unit including a plurality of current sources and a plurality of cascode units, each current source being connected to a cascode unit; a sub-digital to analog converting unit including a current source connected to a plurality of cascode units; a first cascode bias unit, operatively connected to each cascode unit of the main digital to analog converting unit, to bias each current source of the main digital to analog converting unit to operate at a same drain voltage, a second cascode bias unit, operatively connected to each cascode unit of the sub-digital to analog converting unit, to bias the current source of the sub-digital to analog converting unit to operate at a same drain voltage; and a reference voltage source, operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit, to cause the operating emitter/source to collector/drain voltage of each current source of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source of the sub-digital to analog converting unit.
A second aspect of the present invention is a digital to analog converter circuit. The digital to analog converter circuit includes a main digital to analog converting unit including a plurality of current source transistors and a plurality of cascode transistors, each current source transistor being connected to a cascode transistor; a sub-digital to analog converting unit including a current source transistor connected to a plurality of cascode transistors; a first cascode bias unit, operatively connected to a control terminal of each cascode transistor of the main digital to analog converting unit, to bias each current source of the main digital to analog converting unit to operate at a same drain voltage; a second cascode bias unit, operatively connected to a control terminal of each cascode transistor of the sub-digital to analog converting unit, to bias the current source transistor of the sub-digital to analog converting unit to operate at a same source to drain voltage; and a reference voltage source, operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit, to cause the operating emitter/source to collector/drain voltage of each current source transistor of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source transistor of the sub-digital to analog converting unit.